Please refer to data sheets for detailed information. To select how PB3 and PB4 should be used, the jumpers labeled PB3 and PB4 must be set correctly. Description. The AT45DBD is a volt, dual-interface sequential access Flash memory ideally suited for a wide variety of digital voice-, image-, program. Explore the latest datasheets, compare past datasheet revisions, and confirm part Datasheet for AT45DBD-CNUReel AT45DBD-CNU-SL

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To allow for simple in-system reprogrammability, the AT45DBD does not require high input voltages for programming. The device operates from a single power supply, 2. The busy status indicates that the Flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed.

Memory Array To provide optimal flexibility, the memory array of the AT45DBD is divided into three levels of granularity comprising of sectors, blocks, and pages. All program operations to the DataFlash occur on a page by page basis The first 13 bits PA12 – PA0 of the bit address sequence specify which page of the main memory array to read, and the last 11 bits BA10 – BA0 of the bit address sequence specify the starting byte address within the page.

To perform a contin- uous read with the page size set to bytes, the opcode, 03H, must be clocked into the device followed by three address bytes A22 – A To perform a buffer to main memory page program with built-in erase for the The entire main memory can be erased at one time by using the Chip Erase command. Since the entire memory array erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored The status of whether or not sector protection has been enabled or disabled by either the software or the hardware controlled methods can be deter- mined by checking the Status Register.

Software Sector Protection 8. To enable the sector protection using the The Sector Protection Register can be reprogrammed while the sector protection enabled or dis- abled.

Being able to reprogram the Sector Protection Register with the sector protection enabled allows the user to temporarily disable the sector protection to an individual sector rather than dis- abling sector protection completely. Therefore, the contents of the buffer will be altered from its previous state when this command is issued.


Sector Lockdown com- mand if necessary. Command Sector Lockdown Figure Reading the Sector Lockdown Register The Sector Lockdown Register can be read to determine which sectors in the memory array are permanently locked down. Therefore not possible to only program the first two bytes of the register and then pro- gram the remaining 62 bytes at a later time. The device density is indicated using bits and 2 of the status register.


For the AT45DBD, the four bits are The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices Deep Power-down, the device will return to the normal standby mode. Command Resume from Deep Power-down Figure Configuration Register is a user-programmable nonvolatile regis- ter that allows the page size of the main memory to be configured for binary page size bytes or standard DataFlash dataasheet size bytes.

Manufacturer ID codes that are two, three or even four bytes long with the first byte s in the sequence being 7FH. For Atmel and some other manufacturersthe Manufacturer ID data is comprised of only one byte. Main Memory Page to Buffer 1 or 2 Transfer 6. Main Memory Page to Buffer 1 or 2 Compare 7. Main Memory Page Program through Buffer 1 or 2 At45db6642d Page Rewrite Group C commands consist of: Fixed tim- ing is not recommended.

Output Test Load AC Waveforms Six different timing waveforms are shown below. Utilizing the RapidS To take advantage of the RapidS function’s ability to operate at higher clock frequencies, a full clock cycle must be used to transmit data back and forth across the serial bus. The DataFlash is designed to Slave clocks out BYTE a first output byte.

Master clocks in BYTE a. Master clocks adtasheet BYTE h last output byte. Read Operations The following block diagram and waveforms illustrate the various read sequences available. Main Memory Page Read Opcode: This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by- page page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program at45db64d2.


The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10, cumulative page erase and program operations have accumulated before rewriting all pages of the sector. The shipping carrier option is not marked on the devices.

Standard parts are shipped with the page size set to bytes. The user is able to datashret these parts to a byte page size if desired.

AT45DBD-TU Atmel, AT45DBD-TU Datasheet

Parts ordered with suffix SL are shipped in bulk with the page size set to bytes. Parts will have a or SL marked on them Dimensions D1 and E do not include mold protrusion. The surface finish of the package shall be EDM Charmille Unless otherwise specified tolerance: VCSL Changed t from max. PUW Changed t from max Use Block Erase opcode 50H alternative. The Block Erase function is not affected by the Chip Erase issue.

Please contact Atmel for the estimated availability of devices with the fix. The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products.

Elcodis is a trademark of Elcodis Company Ltd. All other trademarks are the property of their respective owners. Download datasheet 2Mb Share this page. Copy your embed code and put on your site: Page 13 Software Sector Protection 8. Page 21 Figure Page 31 Table Page 35 Table Page 37 Output Test Load Page 39 Utilizing the RapidS To take advantage of the RapidS function’s ability to operate at higher clock frequencies, a full clock cycle must be used to transmit data back and forth across the serial bus.

Page 53 Packaging Information